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data sheet 1 1999-05-18 2-phase stepper-motor driver bipolar-ic tle 4728 g p-dso-24-3 ? error-flag for overload, open load, overtemperature ? smd package p-dso-24-3 description tle 4728 g is a bipolar, monolithic ic for driving bipolar stepper motors, dc motors and other inductive loads that operate by constant current. the control logic and power output stages for two bipolar windings are integrated on a single chip which permits switched current control of motors with 0.7 a per phase at operating voltages up to 16 v. the direction and value of current are programmable for each phase via separate control inputs. a common oscillator generates the timing for the current control and turn-on with phase offset of the two output stages. the two output stages in full-bridge configuration include fast integrated free wheeling diodes and are free of crossover current. the device can be driven directly by a microprocessor in several modes by programming phase direction and current control of each bridge independently. with the two error outputs the tle 4728 g signals malfunction of the device. setting the control inputs high resets the error flag and by reactivating the bridges one by one the location of the error can be found. type ordering code package tle 4728 g q67006-a9077 p-dso-24-3 overview features ?2 0.7 amp. full bridge outputs ? integrated driver, control logic and current control (chopper) ? fast free-wheeling diodes ? max. supply voltage 45 v ? output stages are free of crossover current ? offset-phase turn-on of output stages ? all outputs short-circuit proof
tle 4728 g data sheet 2 1999-05-18 figure 1 pin configuration (top view) iep01211 q12 12 13 q22 11 14 error 2 10 15 9 16 q21 8 17 gnd 718 619 gnd 5 20 osc 4 21 phase 1 3 22 223 i 124 gnd gnd error 1 10 11 i gnd gnd gnd q11 r 1 v s + 2 r i 21 20 i gnd phase 2 tle 4728 g
tle 4728 g data sheet 3 1999-05-18 pin definitions and functions pin no. function 1, 2, 23, 24 digital control inputs i x0, i x1 for the magnitude of the current of the particular phase. 1) no current in both bridges inhibits the circuit and current consumption will sink below 3 ma 3 input phase 1; controls the current through phase winding 1. on h-potential the phase current flows from q11 to q12, on l-potential in the reverse direction. 5 ... 8, 17 ... 20 ground; all pins are connected at leadframe internally. 4 oscillator; works at approx. 25 khz if this pin is wired to ground across 2.2 nf. 10 resistor r 1 for sensing the current in phase 1. 9, 12 push-pull outputs q11, q12 for phase 1 with integrated free-wheeling diodes. 11 supply voltage; block to ground, as close as possible to the ic, with a stable electrolytic capacitor of at least 47 m f in parallel with a ceramic capacitor of 100 nf. 14 error 2 output; signals with low the errors: short circuit to ground of one or more outputs or overtemperature. 13, 16 push-pull outputs q22, q21 for phase 2 with integrated free-wheeling diodes. 15 resistor r 2 for sensing the current in phase 2. i set = 450 ma with r sense = 1 w i x1 i x0 phase current example of motor status h h 0 no current 1) h l 0.155 i set hold l h i set normal mode l l 1.55 i set accelerate
tle 4728 g data sheet 4 1999-05-18 figure 2 block diagram 21 error 1 output; signals with low the errors: open load or short circuit to + v s of one or more outputs or short circuit of the load or overtemperature. 22 input phase 2; controls the current flow through phase winding 2. on h-potential the phase current flows from q21 to q22, on l-potential in the reverse direction. pin definitions and functions (contd) pin no. function
tle 4728 g data sheet 5 1999-05-18 note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings t j = C 40 to 150 c parameter symbol limit values unit remarks min. max. supply voltage v s C 0.3 45 v C error outputs v err i err C 0.3 C 45 3 v ma C C output current i q C 1 1 a C ground current i gnd C 2 C a C logic inputs v ixx C 15 15 v i xx; phase 1, 2 oscillator voltage v osc C 0.3 6 v C r 1 , r 2 input voltage v rx C 0.3 5 v C junction temperature t j t j C C 125 150 c c C max. 10,000 h storage temperature t stg C 50 125 cC thermal resistances junction-ambient junction-ambient (soldered on a 35 m m thick 20 cm 2 pc board copper area) junction-case r th ja r th ja r th jc C C C 75 50 15 k/w k/w k/w C C measured on pin 5
tle 4728 g data sheet 6 1999-05-18 note: in the operating range, the functions given in the circuit description are fulfilled. for details see next four pages. these parameters are not 100% tested in production, but guaranteed by design. operating range parameter symbol limit values unit remarks min. max. supply voltage v s 516vC case temperature t c C 40 110 c measured on pin 5 p diss = 2 w output current i q C 800 800 ma C logic inputs v ixx C 5 6 v i xx; phase 1, 2 error outputs v err i err C 0 25 1 v ma C C characteristics v s = 6 to 16 v; t j = C 40 to 130 c parameter symbol limit values unit test condition min. typ. max. current consumption from + v s from + v s i s i s 0.8 20 1.7 30 2.7 50 ma ma i xx = h i xx = l; i q1, 2 = 0 a oscillator output charging current charging threshold discharging threshold frequency i osc v oscl v osch f osc 90 0.8 1.7 18 120 1.3 2.3 24 135 1.9 2.9 30 m a v v khz C C C c osc = 2.2 nf
tle 4728 g data sheet 7 1999-05-18 phase current ( v s = 9 16 v ) mode no current voltage threshold of current comparator at r sense in mode: hold setpoint accelerate i q v ch v cs v ca C 2 40 410 630 0 70 450 700 2 100 510 800 ma mv mv mv i x0 = h; i x1 = h i x0 = l; i x1 = h i x0 = h; i x1 = l i x0 = l; i x1 = l logic inputs ( i x1; i x0; phase x) threshold hysteresis l-input current l-input current h-input current v i v ihy i il i il i ih 1.2 C C 10 C 100 C 1 1.7 50 C 1 C 20 0 2.2 C 1 C 5 10 v mv m a m a m a C C v i = 1.2 v v i = 0 v v i = 5 v error outputs saturation voltage leakage current v errsat i errl 50 C 200 C 500 10 mv m a i err = 1 ma v err = 25 v thermal protection shutdown prealarm delta t jsd t jpa d t j 140 120 10 150 130 20 160 140 30 c c k i q1, 2 = 0 a v err = l d t j = t jsd C t jpa characteristics (contd) v s = 6 to 16 v; t j = C 40 to 130 c parameter symbol limit values unit test condition min. typ. max.
tle 4728 g data sheet 8 1999-05-18 power outputs diode transistor sink pair (d13, t13; d14, t14; d23, t23; d24, t24) saturation voltage saturation voltage reverse current forward voltage forward voltage v sati v sati i ri v fi v fi 0.1 0.2 500 0.6 0.7 0.3 0.5 1000 0.9 1 0.5 0.8 1500 1.2 1.3 v v m a v v i q = C 0.45 a i q = C 0.7 a v s = v q = 40 v i q = 0.45 a i q = 0.7 a diode transistor source pair (t11, d11; t12, d12; t21, d21; t22, d22) saturation voltage saturation voltage saturation voltage saturation voltage reverse current forward voltage forward voltage diode leakage current v satuc v satud v satuc v satud i ru v fu v fu i sl 0.6 0.1 0.7 0.2 400 0.7 0.8 0 1 0.3 1.2 0.5 800 1 1.1 3 1.2 0.6 1.5 0.8 1200 1.3 1.4 10 v v v v m a v v ma i q = 0.45 a; charge i q = 0.45 a; discharge i q = 0.7 a; charge i q = 0.7 a; discharge v s = 40 v, v q = 0 v i q = C 0.45 a i q = C 0.7 a i f = C 0.7 a error output timing time phase x to i xx time i xx to phase x delay phase x to error 2 delay phase x to error 1 delay i xx to error 2 reset delay after phase x reset delay after i xx t pi t ip t pesc t peol t iesc t rp t ri C C C C C C C 5 12 45 15 30 3 1 15 C 80 30 60 10 5 m s m s m s m s m s m s m s C C C C C C C characteristics (contd) v s = 6 to 16 v; t j = C 40 to 130 c parameter symbol limit values unit test condition min. typ. max.
tle 4728 g data sheet 9 1999-05-18 diagrams timing between i xx and phase x to prevent setting the error flag operating conditions: + v s = 14 v, t j = 25 c, i err = 1 ma, load = 3.3 mh, 1 w figure 3 figure 4 t pi iet01888 phase x xx i a) if t pi < typ. 5 m s, an error open load will be set. t ip iet01889 phase x xx i b) if t ip < typ. 12 m s, an error open load will be set.
tle 4728 g data sheet 10 1999-05-18 this time strongly depends on + v s and inductivity of the load, see diagram below. time t ip versus load inductivity propagation delay of the error flag operating conditions: + v s = 14 v, t j = 25 c, i err = 1 ma, load = 3.3 mh, 1 w figure 5 t pesc error 2 iet01883 phase x a) i xx = l, error condition: short circuit to gnd. typ. t pesc : 45 m s
tle 4728 g data sheet 11 1999-05-18 figure 6 figure 7 t peol error 1 iet01884 phase x b) i xx = l, error condition: open load (equivalent: short circuit to + v s ). typ. t peol : 15 m s t iesc iet01885 error 2 xx i c) phase x = h or l, const.; error condition: short circuit to gnd. typ. t iesc : 30 m s t iesc is also measured under the condition: begin of short circuit to gnd till error flag set.
tle 4728 g data sheet 12 1999-05-18 figure 8 figure 9 t rp iet01886 error x phase x d) i xx = l, reset of error flag when error condition is not true. typ. t rp : 3 m s t ri iet01887 error x xx i typ. t ri : 1 m s e) phase x = h or l, const.; reset of error flag when error condition is not true.
tle 4728 g data sheet 13 1999-05-18 quiescent current i s versus supply voltage v s ; bridges not chopping; t j = 25 c oscillator frequency f osc versus junction temperature t j quiesc. current i s versus junct. temp. t j ; bridges not chopping, v s = 14 v output current i qx versus junction temperature t j ied01827 5 0 v ma v s i 10 15 20 40 60 = i qx 0.70 a 20 10 30 50 s 0.45 a 0.07 a -50 15 0 20 v c osc s 150 100 50 c t j osc khz f 25 30 ied01829 = 14 v = 2.2 nf ied01828 -50 0 c ma t s i 0 50 20 40 60 = i qx 0.70 a 150 10 30 50 j 0.50 a 0.07 a 500 -50 0 0 300 100 400 200 r x v s = 14 v 150 100 50 c t j 700 800 600 qx i ma x1 = h, x0 = h i ied01830 i x1 = h, x0 = l ii = 1 w
tle 4728 g data sheet 14 1999-05-18 output saturation voltages v sat versus output current i q typical power dissipation p tot versus output current i q (non stepping) forward current i f of free-wheeling diodes versus forward voltages v f permissible power dissipation p tot versus case temp. t c (measured at pin 5) v 0 0 0.2 0.5 1.0 0.6 0.4 0.8 a i q satud v v satl satuc sat v = 14 v v 1.5 v t j s = 25 c 2.0 ied01831 both phases active 0 0 0.2 1 2 0.6 0.4 0.8 a i q s v = 14 v tot p = 10 mh l osc phase x phase x c 3 t c w r = 25 c = 2.2 nf = 2 4 ied01832 w ied01218 0 0 0.5 1.0 1.5 v 0.2 0.4 0.6 0.8 1.0 a v f i f = 25 ?c v fu v fl t j ied01833 -25 0 w c t tot p 025 75 4 8 12 16 = t jmax 150 c 120 c 125 175 2 6 10 c
tle 4728 g data sheet 15 1999-05-18 input characteristics of i xx , phase x output leakage current -20 = -120 -4 -6 -2 -60 -100 -40 -80 j t 2 06 4 v xx v i 40 c 25 c 150 c xx i i a 0 20 40 phase x xx i ied01834 m 0 -0.8 -0.4 0 0.4 10 20 30 v v q 40 s v = 16 v ma 0.8 i r 1.2 s v = 40 v ied01835
tle 4728 g data sheet 16 1999-05-18 figure 10 application circuit figure 11 test circuit ies01223 phase 1 error 1 phase 2 1 2 3 21 24 23 22 9 12 16 13 11 4 15 10 5, 6, 7, 8, tle 4728g q11 q12 q21 q22 r 2 1 ww 1 1 r 2.2 nf osc gnd m microcontroller 100 nf v s m 100 f +12 v 11 i 10 i 21 i 20 i 14 error 2 17, 18, 19, 20 stepper motor v v v err 2.2 nf osc osc osc i i i i i error err x xx, phase x i rl fu sense v c sl i gnd i gnd r 1 rsense i v fl output v + s q i satu v i v v satl ies01836 ru i 100 nf 100 f s i v s w m tle 4728 g
tle 4728 g data sheet 17 1999-05-18 figure 12 full step operation h l h l h l l h h l l h phase 1 i q1 i q2 phase 2 t t t t t t ied01837 t t accelerate mode normal mode acc i set i - - full step operation i 21 i 20 11 i 10 i acc i set i - acc i - set i i set acc i
tle 4728 g data sheet 18 1999-05-18 figure 13 half step operation ied01838 accelerate mode normal mode half step operation 21 i 20 phase 2 i l l h h h l q2 i - - - i set acc i i set acc i acc i q1 i - phase 1 set i set i l acc i h 10 i 11 i h h l l t t t t t t t t
tle 4728 g data sheet 19 1999-05-18 figure 14 current control in chop-mode v osc h l osc v osc v 0 0 i rsense 1 rsense i 2 v q12 v s + 0 ca v s + v q11 v v + s v q22 + v q21 v s q1 i i acc q2 i t t t t t t t v fu satl v satu d v satu c v phase x phase x operating conditions: v r l s = 14 v = 10 mh = 4 = h phase x ied01839 0 i xx = h w acc i
tle 4728 g data sheet 20 1999-05-18 figure 15 phase reversal and inhibit osc v i rsense 1 s + v q11 v phase 1 i t t t t phase 1 phase 1 operating conditions: v r l s = l for t < = 14 v w = 1 mh = 4 = h for t > ied01840 t t 2.3 v 1.3 v 0 v oscillator high imped. phase change-over h l phase 0 high impedance set i slow current decay set i - 1 t fast current decay = 2x i t 1 1 t i i i 11 11 10 high impedance + v q12 v s slow current decay = l
tle 4728 g data sheet 21 1999-05-18 calculation of power dissipation the total power dissipation p tot is made up of saturation losses p sat (transistor saturation voltage and diode forward voltages), quiescent losses p q (quiescent current times supply voltage) and switching losses p s (turn-on / turn-off operations). the following equations give the power dissipation for chopper operation without phase reversal. this is the worst case, because full current flows for the entire time and switching losses occur in addition. p tot = 2 p sat + p q + 2 p s where p sat @ i n { v sati d + v fu (1 C d ) + v satuc d + v satud ( 1 C d ) } p q = i q v s i n = nominal current (mean value) i q = quiescent current i d = reverse current during turn-on delay i r = peak reverse current t p = conducting time of chopper transistor t on = turn-on time t off = turn-off time t don = turn-on delay t doff = turn-off delay t = cycle duration d = duty cycle t p / t v satl = saturation voltage of sink transistor (tx3, tx4) v satuc = saturation voltage of source transistor (tx1, tx2) during charge cycle v satud = saturation voltage of source transistor (tx1, tx2) during discharge cycle v fu = forward voltage of free-wheeling diode (dx1, dx2) v s = supply voltage p q v s t ------ - i d t don 2 --------------------- - i d i r + () t on 4 ---------------------------------- - i n 2 ---- - t doff t off + () ++ ?t y @
tle 4728 g data sheet 22 1999-05-18 figure 16 figure 17 voltage and current on chopper transistor iet01209 d x 1 d x 2 d x 3 d x 4 t x 2 l t x 4 t x 3 t x 1 r + v s c v sense iet01210 voltage and current at chopper transistor t d t on off t off t p t v satl v sfu v + i d i r i n turn-on turn-off + v fu s v t d on
tle 4728 g data sheet 23 1999-05-18 application hints the tle 4728 g is intended to drive both phases of a stepper motor. special care has been taken to provide high efficiency, robustness and to minimize external components. power supply the tle 4728 g will work with supply voltages ranging from 5 v to 16 v at pin v s . surges exceeding 16 v at v s wont harm the circuit up to 45 v, but whole function is not guaranteed. as soon as the voltage drops below approximately 16 v the tle 4728 g works promptly again. as the circuit operates with chopper regulation of the current, interference generation problems can arise in some applications. therefore the power supply should be decoupled by a 0.1 m f ceramic capacitor located near the package. unstabilized supplies may even afford higher capacities. current sensing the current in the windings of the stepper motor is sensed by the voltage drop across r sense . depending on the selected current internal comparators will turn off the sink transistor as soon as the voltage drop reaches certain thresholds (typical 0 v, 0.07 v, 0.45 v and 0.7 v). these thresholds are not affected by variations of v s . consequently unstabilized supplies will not affect the performance of the regulation. for precise current level it must be considered, that internal bounding wire (typ. 60 m w) is a part of r sense . due to chopper control fast current rises (up to 10 a/ m s) will occur at the sensing resistors. to prevent malfunction of the current sensing mechanism r sense should be pure ohmic. the resistors should be wired to gnd as directly as possible. capacitive loads such as long cables (with high wire to wire capacity) to the motor should be avoided for the same reason. synchronizing several choppers in some applications synchrone chopping of several stepper motor drivers may be desirable to reduce acoustic interference. this can be done by forcing the oscillator of the tle 4728 g by a pulse generator overdriving the oscillator loading currents (approximately 120 m a). in these applications low level should be between 0 v and 0.8 v while high level should between 3 v and 5 v. optimizing noise immunity unused inputs should always be wired to proper voltage levels in order to obtain highest possible noise immunity. to prevent crossconduction of the output stages the tle 4728 g uses a special break before make timing of the power transistors. this timing circuit can be triggered by short glitches (some hundred nanoseconds) at the phase inputs causing the output stage to become high resistive during some microseconds. this will lead to a fast current decay
tle 4728 g data sheet 24 1999-05-18 during that time. to achieve maximum current accuracy such glitches at the phase inputs should be avoided by proper control signals. to lower emi a ceramic capacitor of max. 3 nf is advisable from each output to gnd. thermal shut down to protect the circuit against thermal destruction, thermal shut down has been implemented. error monitoring the error outputs signal corresponding to the logic table the errors described below. logic table overtemperature is implemented as pre-alarm; it appears approximately 20 k before thermal shut down. to detect an open load , the recirculation of the inductive load is watched. if there is no recirculation after a phase change-over, an internal error flipflop is set. because in most kinds of short circuits there wont flow any current through the motor, there will be no recirculation after a phase change-over, and the error flipflop for open load will be set, too. additionally an open load error is signaled after a phase change-over during hold mode. only in the case of a short circuit to gnd , the most probably kind of a short circuit in automotive applications, the malfunction is signaled dominant (see d) in logic table) by a separate error flag. simultaneously the output current is disabled after 30 m s to prevent disturbances. a phase change-over or putting both current control inputs of the affected bridge on high potential resets the error flipflop. being a separate flipflop for every bridge, the error can be located in easy way. kind of error error output error 1 error 2 a) no error h h b) short circuit to gnd h l c) open load 1) 1) also possible: short circuit to + v s or short circuit of the load. lh d) b) and c) simultaneously h l e) temperature pre-alarm l l
tle 4728 g data sheet 25 1999-05-18 package outlines p-dso-24-3 (plastic dual small outline package) 15.6 -0.4 24 13 112 index marking 1) 1.27 2) 0.35 +0.15 0.2 24x -0.2 2.65 max 0.1 0.2 -0.1 2.45 1) -0.2 7.6 0.35 x 45? 8? max 0.23 +0.09 10.3 0.3 0.4 +0.8 1) does not include plastic or metal protrusions of 0.15 max rer side 2) does not include dambar protrusion of 0.05 max per side gps05144 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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